MC68340 datasheet(254/441 Pages) FREESCALE

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6- 4

MC68340 USER’S MANUAL

MOTOROLA

6.2 DMA MODULE SIGNAL DEFINITIONS

This section contains a brief description of the DMA module signals used to provide

handshake control for either a source or destination external device.

NOTE

The terms

assertion and negation are used throughout this

section to avoid confusion when dealing with a mixture of

active-low and active-high signals. The term

assert or assertion

indicates that a signal is active or true, independent of the level

represented by a high or low voltage. The term

negate or

negation indicates that a signal is inactive or false.

6.2.1 DMA Request (

DREQ

≈)

This active-low input is asserted by a peripheral device to request an operand transfer

between that peripheral and memory. The assertion of

DREQ

≈ starts the DMA process.

The assertion level in external burst mode is level sensitive; in external cycle steal mode,

it is falling-edge sensitive.

6.2.2 DMA Acknowledge (

DACK

≈)

This active-low output is asserted by the DMA to signal to a peripheral that an operand is

being transferred in response to a previous transfer request.

6.2.3 DMA Done (

DONE

≈)

This active-low bidirectional signal is asserted by the DMA or a peripheral device during

any DMA bus cycle to indicate that the last data transfer is being performed.

DONE

≈ is an

active input in any mode. As an output,

DONE

≈ is only active in external request mode. An

external pullup resistor is required even if operating only in the internal request mode.

6.3 TRANSFER REQUEST GENERATION

The DMA channel supports two types of request generation methods: internal and

external. Internally generated requests can be programmed to limit the amount of bus

utilization. Externally generated requests can be either burst mode or cycle steal mode.

The request generation method used for the channel is programmed by the channel

control register (CCR) in the REQ field.

6.3.1 Internal Request Generation

Internal requests are accessed in two clocks by the intermodule bus (IMB). The channel is

started as soon as the STR bit in the CCR is set. The channel immediately requests the

bus and begins transferring data. Only internal requests can limit the amount of bus

utilization. The percentage of the bandwidth that the DMA channel can use during a

transfer can be selected by the CCR BB field.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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