NB2304A

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2

Figure 1. Basic Block Diagram

(see Figures 11 and 12 for device specific Block Diagrams)

FBK

CLKA1

CLKA2

CLKB1

CLKB2

REF

PLL

Extra Divider (−2)

B2

Device

Feedback From

Bank A Frequency

Bank B Frequency

NB2304Ax1

Bank A or Bank B

Reference

Reference

NB2304Ax1H

Bank A or Bank B

Reference

Reference

NB2304Ax2

Bank A

Reference

Reference B2

NB2304Ax2

Bank B

2 X Reference

Reference

Figure 2. Pin Configuration

1

2

3

4

8

7

6

5

REF

CLKA1

CLKA2

GND

FBK

CLKB2

CLKB1

NB2304A

Table 2. PIN DESCRIPTION

Pin #

Pin Name

Description

1

REF (Note 1)

Input reference frequency, 5 V

tolerant input.

2

CLKA1 (Note 2) Buffered clock output, Bank A.

3

CLKA2 (Note 2) Buffered clock output, Bank A.

4

GND

Ground.

5

CLKB1 (Note 2) Buffered clock output, Bank B.

6

CLKB2 (Note 2) Buffered clock output, Bank B.

7

3.3 V supply.

8

FBK

PLL feedback input.

1. Weak pulldown.

2. Weak pulldown on all outputs.