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NB6L14 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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NB6L14 bảng dữ liệu(HTML) 1 Page - ON Semiconductor |
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1 / 10 page ![]() © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 0 1 Publication Order Number: NB6L14/D NB6L14 2.5 V/3.3 V3.0 GHz Differential 1:4 LVPECL Fanout Buffer Multi−Level Inputs with Internal Termination Description The NB6L14 is a 3.0 GHz differential 1:4 LVPECL fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB6L14 to accept various logic standards, such as LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The VREF_AC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. The 1:4 fanout design was optimized for low output skew applications. The NB6L14 is a member of the ECLinPS MAX ™ family of high performance clock and data products. Features • Maximum Input Clock Frequency > 2.5 GHz, Typical • < 20 ps Within Device Output Skew • 330 ps Typical Propagation Delay • 145 ps Typical Rise and Fall Times • Differential LVPECL Outputs, 720 mV Amplitude, Typical • LVPECL Mode Operating Range: VCC = 2.375 V to 3.63 V with GND = 0 V • Internal 50 W Input Termination Resistors Provided • VREF_AC Reference Output Voltage • −40°C to +85°C Ambient Operating Temperature • Available in 3 mm x 3 mm 16 Pin QFN • These are Pb−Free Devices MARKING DIAGRAM* http://onsemi.com QFN−16 MN SUFFIX CASE 485G NB6L 14 ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 16 1 *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ORDERING INFORMATION Q D Figure 1. Simplified Logic Diagram |
Số phần tương tự - NB6L14 |
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Mô tả tương tự - NB6L14 |
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