Nexperia

74LVC16373A; 74LVCH16373A

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1OE, 2OE

1, 24

output enable input (active LOW)

1LE, 2LE

48, 25

latch enable input (active HIGH)

GND

4, 10, 15, 21, 28, 34, 39, 45

ground (0 V)

VCC

7, 18, 31, 42

supply voltage

1Q0 to 1Q7

2, 3, 5, 6, 8, 9, 11, 12

data output

2Q0 to 2Q7

13, 14, 16, 17, 19, 20, 22, 23

data output

1D0 to 1D7

47, 46, 44, 43, 41, 40, 38, 37

data input

2D0 to 2D7

36, 35, 33, 32, 30, 29, 27, 26

data input

6. Functional description

Table 3. Function table

Per section of eight bits.

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition

L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition

Z = high-impedance OFF-state

Input

Operating modes

nOE

nLE

nDn

Internal latch

Output

nQ0 to nQ7

L

H

L

L

L

Enable and read register

(transparent mode)

L

H

H

H

H

L

L

l

L

L

Latch and read register

L

L

h

H

H

H

L

l

L

Z

Latch register and disable outputs

H

L

h

H

Z

74LVC_LVCH16373A

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Product data sheet

Rev. 10 — 1 October 2021

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