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SLG84901 bảng dữ liệu(PDF) 13 Page - Renesas Technology Corp

tên linh kiện SLG84901
Giải thích chi tiết về linh kiện  Clock Synthesizer for Intel PCI-Express Gen3 Chipset
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SLG84901 bảng dữ liệu(HTML) 13 Page - Renesas Technology Corp

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1
Page 13 of 21
SLG84901
AC Electrical Characteristics
Differential Outputs (CPU, SRC, DOT_96) Timing Characteristics
Symbol
Description
Min.
Max.
Unit
Conditions
Laccurracy
Long term accuracy
100
ppm
Using frequency counter with the measure-
ment interval equal or greater than 0.15 sec-
ond
Tperiod
Average CPU Period (100MHz, SSC enabled)
9.99906
10.05107
ns
Average period over 1 us
Tperiod
Average CPU Period (133MHz, SSC enabled)
7.44930
7.53830
ns
Average period over 1 us
Tperiod
Average SRC Period (100MHz, SSC enabled)
9.99906
10.05107
ns
Average period over 1 us
Tperiod
Average DOT_96 Period (96MHz)
10.41354
10.41979
ns
Average period over 1 us
Tabs
Absolute Min/Max CPU Period (100, SSC disabled)
9.94900
10.05100
ns
Tabs
Absolute Min/Max CPU Period (133, SSC disabled)
7.44925
7.55075
ns
Tabs
Absolute Min/Max CPU Period (100, SSC enabled)
9.94906
10.10107
ns
Tabs
Absolute Min/Max CPU Period (133, SSC enabled)
7.44930
7.58830
ns
Tabs
Absolute Min/Max SRC Period (100, SSC disabled)
9.94900
10.05100
ns
Tabs
Absolute Min/Max SRC Period (100, SSC enabled)
9.94906
10.10107
ns
Tabs
Absolute Min/Max NS_SRC Period (SSC enabled)
9.94900
10.05100
ns
Tabs
Absolute Min/Max NS_SAS Period (SSC disabled)
9.94900
10.05100
ns
Tabs
Absolute Min/Max DOT_96 Period (96MHz)
10.16563
10.66771
ns
Slew_rise
Rising slew rate
1.0
4.0
V/ns
1. Use ‘average’ acquisition mode of the scope
2. Measurement taken from differential wave-
form
3. Slew rate measured through V_swing volt-
age range centered about differential zero
Slew_fall
Falling slew rate
1.0
4.0
V/ns
1. Use ‘average’ acquisition mode of the scope
2. Measurement taken from differential wave-
form
3. Slew rate measured through V_swing volt-
age range centered about differential zero
Slew_var
Slew rate matching
20
%
1. Use ‘average’ acquisition mode of the scope
2. Measurement taken from single ended
waveform
3. Matching applies to rising edge rate for
Clock and falling edge rate for Clock#. It is
measured using a +/-75mV window centered
on the average cross point where Clock rising
meets Clock# falling. The median cross point
is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calcu-
lation
V_swing
Differential output swing
300
mV
Measurement taken from differential wave-
form
V_cr
Crossing point voltage
250
550
mV
1. Measurement taken from single ended
waveform
2. V_cross is defined as the voltage where
Clock = Clock#
3. Only applies to the differential rising edge
(i.e. Clock rising and Clock# falling)
V_cr_dlt
Variation of V_cr
140
mV
1. Measurement taken from single ended
waveform
2. V_cross is defined as the voltage where
Clock = Clock#
3. V_cross delta is defined as the total varia-
tion of all crossing voltages of rising Clock and
falling Clock#
Tskew
CPU[0:3] skew
50
ps
Tccjitter
Cycle to Cycle Jitter (CPU)
50
ps
Tccjitter
Cycle to Cycle Jitter (SRC)
50
ps
Tccjitter
Cycle to Cycle Jitter (NS_SAS)
50
ps



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