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SLG74190

NOTES:

1. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#

2. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from -150mV to +150mV on the differential waveform .

Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge Only valid for Rising clock and Falling Clock#.

Signal must be monotonic through the Vol to Voh region for Trise and Tfall

3. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing

4. Test configuration is Rs=33.2 O, Rp=49.9, 2 pF

5. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum specified period

6. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg - 0.700), Vcross(rel) Max = 0.550 - 0.5 (0.700 – Vhavg), (see Figure

3-4 for further clarification)

7. Measurement taken from Single Ended waveform

8. Measurement taken from differential waveform

9. Unless otherwise noted, all specifications in this table apply to all processor frequencies

10. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function

11. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function

12. Overshoot is defined as the absolute value of the maximum voltage

13. Undershoot is defined as the absolute value of the minimum voltage

14. The crossing point must meet the absolute and relative crossing point specifications simultaneously

15.

ΔVcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the maximum allowed variance in Vcross for any

particular system

16. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 100,000,000 Hz, 133,333,333 Hz

17. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz

18. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.

19. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the falling edge rate (average) of clock#

20. Measured with device in PLL mode, in BYPASS mode jitter is additive

21. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall)

22. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8V – 2.0V to the time that stable clocks are output from the

buffer chip (PLL locked)

Differential Outputs Timing Characteristics (Non-SSC Clock Input, DIF, 100MHz, 133MHz)

Symbol

Description

Min.

Max.

Unit

Notes

Tstab

Clock Stabilization Tiime

1.8

ms

22

Laccuracy

Long Accuracy

100

ppm

4, 8, 16

Tabsmin

Absolute Minimum Host CLK Period

-2.5%

ns

4, 5, 8

Edge_rate

Edge Rate

1.0

4.0

ns

2, 4, 8

ΔTrise

Rise time variation

125

ps

4, 7, 18

ΔTfall

Fall time variation

125

ps

4, 7, 18

Rice/Fall

Matching

20%

4, 7, 19, 21

VHigh

Voltage High (typ 0.70V)

660

850

mV

4, 7, 10

VLow

Voltage Low (typ 0.0V)

-150

mV

4, 7, 11

Vcross Abs

Absolute Crossing Point Voltage

250

550

mV

1, 3, 4, 7, 14

Vcross rel

Relative Crossing Point Voltage

Calc

Calc

mV

4, 6, 7, 14

Total

Δ

Vcross

Total Variation of Vcross Over all Edges

140

mV

4, 7, 15

Tccjitter

Cycle to Cycle Jitter

50

ps

4, 8, 20

Duty Cycle

Duty Cycle

45

55

%

4, 8

Vovs

Maximum Voltage (Overshoot)

Vhigh+0.3V

4, 7, 12

Vuds

Maximum Voltage (Undershoot)

Vlow-0.3V

4, 7, 13

Vrb

Ringback Voltage

±0.2

N/A

V

4, 7