13

ICSSSTUB32S868D

Advance Information

08/14/06

Register Timing

†After RST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a

minimum time of tinact max.

CK

Dn, DODTn,

DCKEn

RST#

CSGEN

DCS0#

CK#

Qn, QODTn,

QCKEn

PAR_IN

QERR#

tinact

tRPHL

RST # to Q

tRPLH

RST#

to QERR#

H, L, or X

H or L

DCS1#