ADM1067ASU datasheet(21/32 Pages) AD

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ADM1067

Rev. B | Page 21 of 32

SUPPLY FAULT

DETECTION

LOGIC INPUT CHANGE

OR FAULT DETECTION

VP1

VX5

MONITORING FAULT

DETECTOR

MASK

SENSE

1-BIT FAULT

DETECTOR

FAULT

WARNINGS

MASK

1-BIT FAULT

DETECTOR

FAULT

MASK

SENSE

1-BIT FAULT

DETECTOR

FAULT

Figure 26. Monitoring Fault Detector Block Diagram

Timeout Detector

The timeout detector allows the user to trap a failure to make

proper progress through a power-up or power-down sequence.

In the sample application shown in Figure 24, the timeout next-

state transition is from the EN3V3 and EN2V5 states. For the

EN3V3 state, the signal 3V3ON is asserted upon entry to this

state (on the PDO1 output pin) to turn on a 3.3 V supply. This

supply rail is connected to the VP2 pin, and the sequence detec-

tor looks for the VP2 pin to go above its UV threshold, which is

set in the supply fault detector (SFD) attached to that pin.

The power-up sequence progresses when this change is

detected. If, however, the supply fails (perhaps due to a short

circuit overloading this supply), the timeout block traps the

problem. In this example, if the 3.3 V supply fails within 10 ms,

the SE moves to the DIS3V3 state and turns off this supply by

bringing PDO1 low. It also indicates that a fault has occurred by

taking PDO3 high. Timeout delays from 100 μs to 400 ms can

be programmed.

FAULT AND STATUS REPORTING

The ADM1067 has a fault latch for recording faults. Two registers

are set aside for this purpose, FSTAT1 and FSTAT2. A single bit

is assigned to each input of the device, and a fault on that input

sets the relevant bit. The contents of the fault register can be

read out over the SMBus to determine which input(s) faulted.

The fault register can be enabled/disabled in each state. To latch

data from one state, simply ensure that the fault latch is disabled

in the following state. This ensures that only real faults are

captured and not, for example, undervoltage conditions that

may be present during a power-up or power-down sequence.

The ADM1067 also has a number of status registers. These

include more detailed information, such as whether an

undervoltage or overvoltage fault is present on a particular

input faulted, as well as information on ADC limit faults. Note

that the data in the status registers is not latched in any way and,

therefore, is subject to change at any time.

See the AN-698 Application Note for full details about the

ADM1067 registers.

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