P25Q64U datasheet(40/97 Pages) PUYA

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P25Q64U Datasheet

Puya Semiconductor

Page 40 of 97

10.13 Dual Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched

on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of

SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically

increased to the next higher address after each byte data is shifted out, so the whole memory can be read out

at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached.

Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte

address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can

use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 10-13 Dual Read Mode Sequence (Command 3B)

Command

3BH

CS#

SCLK

High - Z

9 10

28 29 30 31

22 21

24- bit address

MSB

Data Out1

Data Out2

CS#

SCLK

MSB

Dummy Clocks

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

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