COMMERCIALTEMPERATURERANGE

IDTCV126

PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR

13

PD, POWER DOWN

PDisanasynchronousactivehighinputusedtoshutoffallclockscleanlypriortoclockpower. WhenPDisassertedhighall clockswillbedrivenlowbefore

turning off the VCO. In PD de-assertion all clocks will start without glitches.

PD ASSERTION

PD

CPU 133MHz

CPU# 133MHz

SRC 100MHz

SRC# 100MHz

USB 48MHz

PCI 33MHz

REF 14.31818

PD

CPU

CPU#

SRC

SRC#

PCIF/PCI

USB

DOT96

DOT96#

REF

0

Normal

Normal

Normal

Normal

33MHz

48MHz

Normal

Normal

14.318MHz

1IREF * 2 or float

Float

IREF * 2 or float

Float

Low

Low

IREF * 2 or float

Float

Low

PCI STOP FUNCTIONALITY

If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit.

PCI_STOP (Byte 6 bit 3)

CPU

CPU#

SRC

SRC#

PCIF/PCI

48MHz

REF

1

Normal

Normal

Normal

Normal

33MHz

48MHz

14.318MHz

0

Normal

Normal

IREF * 6 or float

Low

Low

48MHz

14.318MHz