9

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MARCH 2013

NOTES:

1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW

during reset will make the pin act as a load enable for the programmable flag offset registers.

2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.

3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.

Figure 4. Reset Timing

tRS

tRSR

RSA (RSB)

RENA1, RENA2

(

RENB1, RENB2)

tRSF

tRSF

OEA (OEB) = 1

OEA (OEB) = 0

(2)

EFA, PAEA

(

EFB, PAEB)

FFA, PAFA

(

FFB, PAFB)

QA0 - QA8

(QB0 - QB8)

3034 drw 05

WENA1

(

WENB1)

tRSS

tRSF

tRSR

tRSS

tRSR

tRSS

WENA2/

LDA

(WENB2/

LDB)

(1)

NOTE:

1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time between

the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB) edge.

Figure 5. Write Cycle Timing

tDH

tENH

tSKEW1(1)

tCLK

tCLKH

tCLKL

tDS

tENS

tWFF

tWFF

WCLKA (WCLKB)

DA0 - DA8

(DB0 - DB8)

WENA1

(

WENB1)

WENA2 (WENB2)

(If Applicable)

FFA

(

FFB)

RCLKA (RCLKB)

RENA1, RENA2

(

RENB1, RENB2)

NO OPERATION

NO OPERATION

3034 drw 06

DATA IN VALID

tENS

tENH