2

Integrated

Circuit

Systems, Inc.

ICS954309

1044A—02/20/07

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1GND48

PWR

Ground pin for the 48MHz outputs

2

SRCT0

OUT

True clock of differential SRC clock pair.

3

SRCC0

OUT

Complement clock of differential SRC clock pair.

4OE0#

IN

Active low input for enabling DIF pair 0.

1 = tri-state outputs, 0 = enable outputs

5

SRCT1

OUT

True clock of differential SRC clock pair.

6

SRCC1

OUT

Complement clock of differential SRC clock pair.

7OEA#

IN

Active low input for enabling outputs.

1 = tri-state outputs, 0 = enable outputs

8

SRCT2

OUT

True clock of differential SRC clock pair.

9

SRCC2

OUT

Complement clock of differential SRC clock pair.

10

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal

11

GNDSRC

PWR

Ground pin for the SRC outputs

12

OE3#

IN

Active low input for enabling DIF pair 3.

1 = tri-state outputs, 0 = enable outputs

13

SRCT3

OUT

True clock of differential SRC clock pair.

14

SRCC3

OUT

Complement clock of differential SRC clock pair.

15

OE6#

IN

Active low input for enabling DIF pair 6.

1 = tri-state outputs, 0 = enable outputs

16

PCI_STOP#

IN

Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not

effected by this input.

17

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal

18

SRCT5

OUT

True clock of differential SRC clock pair.

19

SRCC5

OUT

Complement clock of differential SRC clock pair.

20

SRCC6

OUT

Complement clock of differential push-pull SRC clock pair.

21

SRCT6

OUT

True clock of differential push-pull SRC clock pair.

22

SRCT8

OUT

True clock of differential SRC clock pair.

23

SRCC8

OUT

Complement clock of differential SRC clock pair.

24

OEB#

IN

Active low input for enabling outputs.

1 = tri-state outputs, 0 = enable outputs

25

SRCC9

OUT

Complement clock of differential SRC clock pair.

26

SRCT9

OUT

True clock of differential push-pull SRC clock pair.

27

SRCT10

OUT

True clock of differential push-pull SRC clock pair.

28

SRCC10

OUT

Complement clock of differential SRC clock pair.

29

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal

30

GNDSRC

PWR

Ground pin for the SRC outputs

31

CPUCLKC2_ITP/SRCCLKC7

OUT

Complementary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output.

These are current mode outputs. External resistors are required for voltage bias.

Selected by ITP_EN input.

32

CPUCLKT2_ITP/SRCCLKT7

OUT

True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are

current mode outputs. External resistors are required for voltage bias. Selected

by ITP_EN input.