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ICS952011 bảng dữ liệu(PDF) 14 Page - Renesas Technology Corp

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14
Integrated
Circuit
Systems, Inc.
ICS952011
0721A—07/29/03
I
2C Table: Output Control Register
Control
Function
Bit 7
PCICLK_F1
Output Control
RW
Disable
Enable
1
Bit 6
PCICLK_F0
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK0
Output Control
RW
Disable
Enable
1
I
2C Table: Byte Count Register
Control
Function
Bit 7
BC7
RW
-
-
0
Bit 6
BC6
RW
-
-
0
Bit 5
BC5
RW
-
-
0
Bit 4
BC4
RW
-
-
0
Bit 3
BC3
RW
-
-
1
Bit 2
BC2
RW
-
-
1
Bit 1
BC1
RW
-
-
1
Bit 0
BC0
RW
-
-
1
I
2C Table: Watchdog Timer Register
Control
Function
Bit 7
WD7
RW
-
-
0
Bit 6
WD6
RW
-
-
0
Bit 5
WD5
RW
-
-
0
Bit 4
WD4
RW
-
-
1
Bit 3
WD3
RW
-
-
0
Bit 2
WD2
RW
-
-
0
Bit 1
WD1
RW
-
-
0
Bit 0
WD0
RW
-
-
0
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Bit 6
WDEN
Watchdog Enable
R
Disable
Enable
0
Bit 5
Reserved
Reserved
RW
-
-
0
Bit 4
WD SF4
RW
-
-
0
Bit 3
WD SF3
RW
-
-
0
Bit 2
WD SF2
RW
-
-
0
Bit 1
WD SF1
RW
-
-
0
Bit 0
WD SF0
RW
-
-
1
Type
Type
0
Byte 9
Pin #
Name
-
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 16 X 290ms
=4.64 seconds
-
-
-
-
1
01
0
PWD
PWD
1
PWD
15
Type
Name
0
1
14
23
22
Byte 7
Pin #
Byte 8
Pin #
Name
21
20
17
16
PWD
-
Writing to this register will
configure how many
bytes will be read back,
default is 0F = 15 bytes.
-
-
-
-
-
-
-
Writing to these bit will
configure the safe
frequency as Byte4bit 2,
(7:4)
Name
Type
0
M/NEN
M/N Programming
Enable
Enable
Disable
-
-
-
RW
Byte 10
Pin #
Bit 7
-
-
-
-
-
-
-
-



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