16

Integrated

Circuit

Systems, Inc.

ICS951104

Preliminary Product Preview

0485G—10/13/05

The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low

in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising

edge.

Assertion of PCI_STOP# Waveforms

PCI_STOP# - Assertion (transition from logic "1" to logic "0")

CPU_STOP# - Assertion (transition from logic "1" to logic "0")

Assertion of CPU_STOP# Waveforms

The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I

2C configuration to be stoppable via

assertion of CPU_STOP# are to be stopped after their next transition. When the I

2C Bit 6 of Byte 1 is programmed to '0' the final

state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values.

The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the

I

2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not

be driven.

CPU_STOP#

CPUCLKT

CPUCLKC

PCI_STOP#

PCI_F

PCI

Tsu 10ns min