ICS950818

CPU_STOP# - De-assertion (transition from logic "O" to logic "1")

All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from

the de-assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the

SMBus Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop#

de-assertion.

De-assertion of CPU_STOP# Waveforms

CPU_STOP#

====i=�===;--;::::::;--;:::::::;-;:::::::--;:::::-;::::;--;::::::;--;::::::;--;:::::::--;:::::-;::::;--;::::::;--;:�;::::::;

CPUCLKT(2:0)

Tdrive_CPU_STOP# <10ns@200mV

*CPUCLKT(2:0)TS

*Signal TS is CPUCLKT in Tri-State mode

PD# - Assertion (transition from logic "1" to logic "O")

When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU

clocks must be held low on their next high to low transitions. When the SMBUS Bit 6 of Byte O is programmed to 'O'

CPU clocks must be held with the CPU clock pin driven high with a value of 2 x lref, and CPU# undriven. If Bit 6 of

Byte O is '1' then both CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte

0 = 'O', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.

Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than

one clock cycle to complete.

Power Down Assertion of Waveforms

I Ons

1

PD#

CPUCLKT 100MHz

CPUCLKC 100MHz

3V66MHz 1---.....

PCICLK 33MHz

USB48MHz

REF 14.318MHz

PD# Functionality

PD#

CPUCLKT

1

Normal

0

iref * Mult

0825F-11/19/03

CPUCLKC

Normal

Float

1 son�

3V66

PCICLK_F

USB/DOT

PCICLK

48MHz

66MHz

33MHz

48MHz

Low

Low

Low

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