IDTTM Frequency Generator with 200MHz Differential CPU Clocks

0542

K—03/23/16

ICS950812

Frequency Generator with 200MHz Differential CPU Clocks

24

All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no

defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard

skew described below as Tpci.

Un-Buffered Mode 3V66 & PCI Phase Relationship

Group to Group Skews at Common Transition Edges: Unbuffered Mode

GROUP

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

3V66 to PCI

1,2

S3V66-PCI

3V66 (5:0) leads 33MHz PCI

1.5

2.55

3.5

ns

1Guarenteed by design, not 100% tested in production.

2500ps Tolerance

3V66 (1:0)

3V66 (4:2)

3V66_5

E_PCICLK (3,1)

PCICLK_F (2:0) PCICLK (6:0)

Tpci

Tepci

E_ PC IC L K to P C IC L K Sk e w s

GR OU P

S Y M B O L

C ON D IT ION S

M IN

TY P

M A X

U N IT S

T E_PCI-PCI0

E _P C ICLK 1 (pin 11)= 0

E _P C ICLK 3 (pin 13)= 0

-0.2

0

0.2

ns

E_PC IC LK to PC IC LK

1

T E_PCI-PCI1

E _P C ICLK 1 (pin 11)= 0

E _P C ICLK 3 (pin 13)= 1

0.3

0.5

0.7

ns

T E_PCI-PCI2

E _P C ICLK 1 (pin 11)= 1

E _P C ICLK 3 (pin 13)= 0

0.8

1.0

1.2

ns

T E_PCI-PCI3

E _P C ICLK 1 (pin 11)= 1

E _P C ICLK 3 (pin 13)= 1

1.3

1.5

1.7

ns