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ICS8714004I bảng dữ liệu(PDF) 21 Page - Renesas Technology Corp

tên linh kiện ICS8714004I
Giải thích chi tiết về linh kiện  FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet
PDF  32 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS8714004I bảng dữ liệu(HTML) 21 Page - Renesas Technology Corp

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ICS8714004DKI REVISION A MARCH 24, 2014
21
©2014 Integrated Device Technology, Inc.
ICS8714004I Data Sheet
FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k
 resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k
 resistor can be tied from CLK to ground.
MLVDS, nMLVDS Inputs
For applications not requiring the use of the differential input, both
MLVDS and nMLVDS can be left floating. Though not required, but for
additional protection, a 1k
 resistor can be tied from MLVDS to
ground.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
M-LVDS Outputs
All unused M-LVDS output pairs can be either left floating or
terminated with 100
 across. If they are left floating, there should be
no trace attached.



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