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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LP5860RKPR bảng dữ liệu(PDF) 21 Page - Texas Instruments |
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LP5860RKPR bảng dữ liệu(HTML) 21 Page - Texas Instruments |
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21 / 71 page  SCL SDA 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 8 9 1 CA4 CA3 CA2 CA1 CA0 RA9 RA8 W ACK RA7 RA6 RA0 ACK D7 D0 ACK D7 Address Byte 1 Address Byte 2 RA5 RA4 RA3 RA2 RA1 8 9 D0 NACK Start Stop Data Byte 2 10 1 2 3 4 5 6 7 8 9 CA4 CA3 CA2 CA1 CA0 RA9 RA8 R ACK Address Byte 1 Restart Data Byte 1 Figure 8-12. I2C Read Timing Multiple Devices Connection The LP5861T enters into I2C mode if IFS is connected to GND. The ADDR0/1 pin is used to select the unique I2C follower address for each device. The SCL and SDA lines must each have a pullup resistor (4.7 KΩ for 400 KHz, 2 KΩ for 1 MHz) placed somewhere on the line and remain HIGH even when the bus is idle. VIO_EN can either be connected with VIO power supply or GPIO. TI suggests to put one 1-nF cap as closer to VIO_EN pin as possible. Up to four LP5861T follower devices can share the same I2C bus by the different ADDR configurations. VIO_EN SDA SCL MCU GND Device 0 ADDR0 ADDR1 VIO EN SDA SCL VIO Device 1 ADDR0 ADDR1 VSYNC VIO_EN SDA SCL GND Device N (N=1,2,3) ADDR0 ADDR1 VSYNC IFS IFS Figure 8-13. I2C Multiple Devices Connection SPI Interface The LP5861T is compatible with SPI serial-bus specification, and it operates as a follower. The maximum frequency supported by LP5861T is 12 MHz. SPI Data Transactions MISO output is normally in a high impedance state. When the follower-select pin SS for the device is active (low) the MISO output is pulled low for read only. During write cycle MISO stays in high-impedance state. The follower-select signal SS must be low during the cycle transmission. SS resets the interface when high. Data is clocked in on the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK. SPI Data Format The address and data bits are transmitted MSB first with 8-bits length format in each cycle. Each transmission is started with Address Byte 1, which contains 8 higher bits of the register address. The Address Byte 2 is started with 2 lower bits of the register address and 1 read and write bit. The auto-increment feature allows writing and www.ti.com LP5861T SNVSCE4 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LP5861T |
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