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AM26LS32AM bảng dữ liệu(PDF) 12 Page - Texas Instruments |
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AM26LS32AM bảng dữ liệu(HTML) 12 Page - Texas Instruments |
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12 / 36 page ![]() Copyright © 2016, Texas Instruments Incorporated 12 AM26LS32AC, AM26LS32AI, AM26LS32AM AM26LS33AC, AM26LS33AM SLLS115F – OCTOBER 1980 – REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM Submit Documentation Feedback Copyright © 1980–2016, Texas Instruments Incorporated 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information When using AM26LS32A as a receiver, the AM26LS31AC can allow multiple AM26LS32As to be used causing an increase in the amount of outputs. 9.2 Typical Application Figure 17 shows a configuration with no termination. Although reflections are present at the receiver inputs at a data signaling rate of 200 kbps with no termination, the RS-422-compliant receiver reads only the input differential voltage and produces a clean signal at the output. †R T equals the characteristic impedance of the line. Figure 17. Application Diagram 9.2.1 Design Requirements Resistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary from system to system. For example, the termination resistor, RT, must be within 20% of the characteristic impedance, ZO, of the cable and can vary from about 80 Ω to 120 Ω. 9.2.2 Detailed Design Procedure Add a VCC bypass capacitor (0.1 µF or more). Either enable (G pin) input can turn on the receivers, so connect the desired enable to a compatible logic line output. The other enable input must be tied to the inactive state supply rail. If the receivers must always be active, then connect both enables to the supply rail such that at least one is set to an active-state rail. VCC must be 5 V within 10% and logic inputs must provide TTL-compatible voltage levels A & B Inputs can lead to an external connector or can be left unconnected. The last receiver on a cable requires termination, either on-board or use as an external resistor. Unused Y outputs can be left unconnected. |
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