7

Integrated

Circuit

Systems, Inc.

ICS950219

Preliminary Product Preview

0640D—12/30/03

Byte 1: Output Control Register

(1 = enable, 0 = disable)

Byte 3: Output Control Register

(1 = enable, 0 = disable)

Byte 2: Output Control Register

(1 = enable, 0 = disable)

Byte 4: Output Control Register

(1 = enable, 0 = disable)

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B4

4

,

5

41

2

C

/

T

U

P

C

6

t

i

B7

3

,

8

31

1

C

/

T

U

P

C

5

t

i

B0

4

,

1

41

0

C

/

T

U

P

C

4

t

i

B-

X

k

c

a

b

d

a

e

R

4

S

F

3

t

i

B-

X

k

c

a

b

d

a

e

R

3

S

F

2

t

i

B-

X

k

c

a

b

d

a

e

R

2

S

F

1

t

i

B-

X

k

c

a

b

d

a

e

R

1

S

F

0

t

i

B-

X

k

c

a

b

d

a

e

R

0

S

F

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B7

11

9

_

K

L

C

I

C

P

5

t

i

B6

11

8

_

K

L

C

I

C

P

4

t

i

B5

11

7

_

K

L

C

I

C

P

3

t

i

B4

11

6

_

K

L

C

I

C

P

2

t

i

B2

11

5

_

K

L

C

I

C

P

1

t

i

B1

11

4

_

K

L

C

I

C

P

0

t

i

B0

11

3

_

K

L

C

I

C

P

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B-

X

)

k

c

a

b

d

a

e

r

(

0

L

E

S

i

t

l

u

M

6

t

i

B-

X

)

k

c

a

b

d

a

e

R

(

1

L

E

S

i

t

l

u

M

5

t

i

B1

31

0

-

6

6

V

3

4

t

i

B0

31

1

-

6

6

V

3

3

t

i

B8

41

0

F

E

R

2

t

i

B1

1

1

F

E

R

1

t

i

B7

21

3

_

6

6

V

3

0

t

i

B8

21

2

_

6

6

V

3

Notes:

1. PWD = Power on Default

2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,

CPUCLKC off, and external resistor termination will bring CPUCLKC low.

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B3

21

1

_

z

H

M

8

4

6

t

i

B2

21

0

_

z

H

M

8

4

5

t

i

B-

1

e

l

b

a

s

i

D

=

0

,

e

l

b

a

n

E

=

1

t

c

e

t

e

d

t

f

i

h

s

r

a

e

g

t

e

s

e

R

4

t

i

B-

X

d

e

v

r

e

s

e

R

3

t

i

B-

0

z

H

M

8

4

=

1

,

z

H

M

4

2

=

0

;

z

H

M

8

4

_

4

2

l

e

S

2

t

i

B8

1

2

_

K

L

C

I

C

P

1

t

i

B7

1

1

_

K

L

C

I

C

P

0

t

i

B6

1

0

_

K

L

C

I

C

P