ICS85214

LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

IDT™ / ICS™ HSTL FANOUT BUFFER

8

ICS85214AG

REV. B

JUNE 3, 2016

Differential Clock Input Interface

The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both VSWING and VOH must meet the VPP

and VCMR input requirements. Figures 3A to 3F show interface

examples for the HiPerClockS CLK/CLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 3A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

Figure 3A. HiPerClockS CLK/CLK Input

Driven by an IDT Open Emitter

HiPerClockS LVHSTL Driver

Figure 3C. HiPerClockS CLK/CLK Input

Driven by a 3.3V LVPECL Driver

Figure 3E. HiPerClockS CLK/CLK Input

Driven by a 3.3V HCSL Driver

Figure 3B. HiPerClockS CLK/CLK Input

Driven by a 3.3V LVPECL Driver

Figure 3D. HiPerClockS CLK/CLK Input

Driven by a 3.3V LVDS Driver

Figure 3F. HiPerClockS CLK/CLK Input

Driven by a 2.5V SSTL Driver

R1

50

Ω

R2

50

Ω

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

HCSL

*R3

*R4

CLK

nCLK

3.3V

3.3V

Differential

Input

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

R1

120

Ω

R2

120

Ω

R3

120

Ω

R4

120

Ω