ICS844004BGI-01 REVISION A MAY 20, 2013

2

©2013 Integrated Device Technology, Inc.

ICS844004I-01 Data Sheet

FEMTOCLOCK™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

Table 1. Pin Descriptions

NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 2

nQ1, Q1

Output

Differential output pair. LVDS interface levels.

3, 22

VDDO

Power

Output supply pins.

4, 5

Q0, nQ0

Output

Differential output pair. LVDS interface levels.

6

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs nQx to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS/LVTTL interface levels.

7

nPLL_SEL

Input

Pulldown

PLL select. Selects between the PLL and REF_CLK as input to the dividers.

When LOW, selects PLL (PLL enabled). When HIGH, the PLL is bypassed.

LVCMOS/LVTTL interface levels.

8, 18

nc

Unused

No connect.

9VDDA

Power

Analog supply pin.

10,

12

F_SEL0,

F_SEL1

Input

Pulldown

Frequency select pins. LVCMOS/LVTTL interface levels.

11

VDD

Power

Core supply pin.

13,

14

XTAL_OUT,

XTAL_IN

Input

Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.

15, 19

GND

Power

Power supply ground.

16

REF_CLK

Input

Pulldown

Single-ended reference clock input. LVCMOS/LVTTL interface levels.

17

nXTAL_SEL

Input

Pulldown

Selects between crystal or REF_CLK inputs as the PLL reference source.

Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.

LVCMOS/LVTTL interface levels.

20, 21

nQ3, Q3

Output

Differential output pair. LVDS interface levels.

23, 24

Q2, nQ2

Output

Differential output pair. LVDS interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

4pF

RPULLDOWN Input Pulldown Resistor

51

k

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