ICS840271I

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

10

ICS840271BGI REV. A APRIL 23, 2009

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS840271I.

Equations and example calculations are also provided.

1.

Power Dissipation.

The total power dissipation for the ICS840271I is the sum of the core power plus the analog power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

•

Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(75mA + 8mA) = 287.6mW

•

Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDD/2

Output Current IOUT = VDD_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 16Ω)] = 26.25mA

•

Power Dissipation on the ROUT per LVCMOS output

Power (ROUT) = ROUT * (IOUT)

2 = 16

Ω * (26.25mA)2 = 11mW per output

Total Power Dissipation

•

Total Power

= Power (core)MAX + Total Power (ROUT)

= 287.6mW + 11mW

= 298.6mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.

The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj =

θ

JA * Pd_total + TA

Tj = Junction Temperature

θ

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance

θ

JA must be used. Assuming no air flow

and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.299W *129.5°C/W = 123.7°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type

of board (multi-layer).

Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection

θ

JA by Velocity

Meters per Second

01

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

129.5°C/W

125.5°C/W

123.5°C/W