ADV7392EBZ datasheet(16/96 Pages) AD

16 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 16 of 96

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

VDD_IO

VDD

DGND

24 RSET

23 COMP

22 DAC 1

21 DAC 2

20 DAC 3

19 VAA

18 AGND

17 PVDD

TOP VIEW

(Not to Scale)

ADV7390/

ADV7391

Figure 17. ADV7390/ADV7391 Pin Configuration

TOP VIEW

(Not to Scale)

ADV7392/

ADV7393

PIN 1

INDICATOR

VDD_IO

VDD

DGND

P10

23 PVDD

24 AGND

25 VAA

26 DAC 3

27 DAC 2

28 DAC 1

29 COMP

30 RSET

22 EXT_LF

21 PGND

Figure 18. ADV7392/ADV7393 Pin Configuration

Table 12. Pin Function Descriptions

Pin Number

ADV7390/91

ADV7392/93

Mnemonic

Input/

Output

Description

9 to 7, 4 to 2,

31, 30

P7 to P0

8-Bit Pixel Port (P7 to P0). P0 is the LSB. Refer to Table 30 for input

modes (ADV7390/ADV7391).

18 to 15, 11 to 8, 5

to 2, 39 to 37, 34

P15 to P0

16-Bit Pixel Port (P15 to P0). P0 is the LSB. Refer to Table 31 for input

modes (ADV7392/ADV7393).

CLKIN

Pixel Clock Input for HD (74.25 MHz), ED1 (27 MHz or 54 MHz), or

SD (27 MHz).

HSYNC

I/O

Horizontal Synchronization Signal. This pin can also be configured to

output an SD, ED, or HD horizontal synchronization signal. See the

External Horizontal and Vertical Synchronization Control section.

VSYNC

I/O

Vertical Synchronization Signal. This pin can also be configured to

output an SD, ED, or HD vertical synchronization signal. See the

External Horizontal and Vertical Synchronization Control section.

SFL/MISO

I/O

Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data

Output (MISO). The SFL input is used to drive the color subcarrier

DDS system, timing reset, or subcarrier reset.

RSET

Controls the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For

full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor

must be connected from RSET to AGND. For low drive operation (for

example, into a 300 Ω load), a 4.12 kΩ resistor must be connected

from RSET to AGND.

COMP

Compensation Pin. Connect a 2.2 nF capacitor from COMP to VAA.

22, 21, 20

28, 27, 26

DAC 1, DAC 2, DAC 3

DAC Outputs. Full-drive and low-drive capable DACs.

SCL/MOSI

Multifunctional Pin: I2C Clock Input/SPI Data Input.

SDA/SCLK

I/O

Multifunctional Pin: I2C Data Input/Output. Also, SPI clock input.

ALSB/SPI_SS

Multifunctional Pin: ALSB sets up the LSB2 of the MPU I2C

address/SPI slave select (SPI_SS).

RESET

Resets the on-chip timing generator and sets the ADV739x into its

default mode.

VAA

Analog Power Supply (3.3 V).

5, 28

6, 35

VDD

Digital Power Supply (1.8 V). For dual-supply configurations, VDD can

be connected to other 1.8 V supplies through a ferrite bead or

suitable filtering.

VDD_IO

Input/Output Digital Power Supply (3.3 V).

PVDD

PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can

be connected to other 1.8 V supplies through a ferrite bead or

suitable filtering.

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