S71GS256 datasheet(165/195 Pages) SPANSION

165 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

165

Ad vance

Info rmat i o n

Notes:

1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes

HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How

Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).

Figure 58. Burst READ Followed by Asynchronous WRITE Using ADV#

Valid

Address

tSP

tHD

tOHZ

High-Z

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

A[22:0]

ADV#

CE#

DQ[15:0]

WAIT

tHD

VIH

VIL

OE#

WE#

tCLK

VIH

VIL

CLK

tSP tHD

(Note 2)

tWP

tWPH

tSP

tHD

Valid

Output

Valid

Input

tCBPH

tKOH

tACLK

Don't Care

Undefined

Legend:

Valid

Address

tAS

VIH

VIL

LB#/UB#

tOLZ

tAVS

tAVH

tCSP

tBW

tDH

tKHTL

tDW

tSP

tHD

tHZ

tBOE

tCEM

tAW

tCW

tVS

tVP

tVPH

tAS

tCEW

tHZ

READ Burst Identified

(WE# = HIGH)

High-Z

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