PCF5271CAB100 datasheet(46/56 Pages) FREESCALE

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MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 13. RESET and Configuration Override Timing

* Refer to the Coldfire Integration Module (CIM) section for more information.

8.9

I2C Input/Output Timing Specifications

Table 35 lists specifications for the I2C input timing parameters shown in Figure 14.

Table 36 lists specifications for the I2C output timing parameters shown in Figure 14.

Table 35. I2C Input Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Min

Max

Units

Start condition hold time

—

tcyc

Clock low period

—

tcyc

I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)

—

Data hold time

—

I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)

—

Clock high time

—

tcyc

Data setup time

—

Start condition setup time (for repeated start condition only)

—

tcyc

Stop condition setup time

—

tcyc

Table 36. I2C Output Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Min

Max

Units

I11

Start condition hold time

—

tcyc

I2 1

Clock low period

—

tcyc

I3 2

I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to

VIH = 2.4 V)

——

µs

I4 1

Data hold time

—

tcyc

I5 3

I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to

VIL =0.5 V)

—3

I6 1

Clock high time

—

tcyc

CLKOUT

RESET

RSTOUT

Configuration Overrides*:

(RCON, Override pins])

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