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STM32H7 bảng dữ liệu(PDF) 312 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  32-bit Arm® Cortex®-M7 480MHz MCUs, up to 2MB flash, up to 1MB RAM, 46 com. and analog interfaces
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Electrical characteristics (rev V)
STM32H742xI/G STM32H743xI/G
312/357
DS12110 Rev 10
Figure 110. MDIO Slave timing diagram
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 209 and Table 210 for SDIO are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage summarized in Table 122: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 0x11
•
Capacitive load CL=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics.
MSv40460V1
tsu(MDIO)
tMDC)
th(MDIO)
td(MDIO)
Table 209. Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
133
MHz
-
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fPP =52MHz
8.5
9.5
-
ns
tW(CKH)
Clock high time
fPP =52MHz
8.5
9.5
-
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tISU
Input setup time HS
-
2.5
-
-
ns
tIH
Input hold time HS
-
0.5
-
-
tIDW(4)
Input valid window (variable window)
-
3
-
-
-
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode
tOV
Output valid time HS
-
-
3.5
5
ns
tOH
Output hold time HS
-
3
-
-



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