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STM32H7 bảng dữ liệu(PDF) 87 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  32-bit Arm® Cortex®-M7 480MHz MCUs, up to 2MB flash, up to 1MB RAM, 46 com. and analog interfaces
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STM32H7 bảng dữ liệu(HTML) 87 Page - STMicroelectronics

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DS12110 Rev 10
87/357
STM32H742xI/G STM32H743xI/G
Pin descriptions
101
-
F7
143
C4
C6
171
203
E7
PDR_ON
I
FT
-
-
-
-F4
-
B4
-
-
-
A6
VDDLDO
(8)
S-
-
-
-
100
-
144
-
C5
172
204
-
VDD
S
-
-
-
-
-
-
-
-
D4
173
205
A4
PI4
I/O
FT_h
-
TIM8_BKIN,
SAI2_MCLK_A,
TIM8_BKIN_COMP12,
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
-
-
-
-
-
C4
174
206
A3
PI5
I/O
FT_h
-
TIM8_CH1,
SAI2_SCK_A,
FMC_NBL3,
DCMI_VSYNC, LCD_B5,
EVENTOUT
-
-
-
-
A4
C3
175
207
A2
PI6
I/O
FT_h
-
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6,
LCD_B6, EVENTOUT
-
-
-
-
E2
C2
176
208
B3
PI7
I/O
FT_h
-
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7,
LCD_B7, EVENTOUT
-
-
-
-
-
H9
-
-
-
VSS
S
-
-
-
-
-
-
-
-
K9
-
-
-
VSS
S
-
-
-
-
-
-
-
-
K10
-
-
M15
VSS
S
-
-
-
-
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. This ball should remain floating.
3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.
4. This ball should be connected to VSS.
5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
7. VREF+ pin, and consequently the internal voltage reference, are not available on the TFBGA100 package. On this package,
this pin is double-bonded to VDDA which can be connected to an external reference. The internal voltage reference buffer is
not available and must be kept disabled
8. When it is not available on a package, the VDDLDO pin is internally tied to VDD.
9. When the pin is used in USB configuration (OTG_HS_ID/OTG_HS_VBUS), the I/O is supplied by VDD33USB, otherwise it is
supplied by VDD.
10. When it is not available on a package, the VDD50USB pin is internally tied to VDD33USB.
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Alternate functions
Additional
functions



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