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ICS1894-44 bảng dữ liệu(PDF) 21 Page - Renesas Technology Corp

tên linh kiện ICS1894-44
Giải thích chi tiết về linh kiện  10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
PDF  54 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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ICS1894-44 bảng dữ liệu(HTML) 21 Page - Renesas Technology Corp

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ICS1894-44
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
PHYCEIVER
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
21
ICS1894-44
REV B 030112
8.3
Message code field
/Unformatted code field
Bit value depends on the
particular message
Bit value depends on the
particular message
RO
–
0
0
8.2
Message code field
/Unformatted code field
Bit value depends on the
particular message
Bit value depends on the
particular message
RO
–
0
8.1
Message code field
/Unformatted code field
Bit value depends on the
particular message
Bit value depends on the
particular message
RO
–
0
8.0
Message code field
/Unformatted code field
Bit value depends on the
particular message
Bit value depends on the
particular message
RO
–
0
Register
9 through 15 - Reserved by IEEE
Register
16 - Extended Control Register
16.15
Command Override
Write enable
Disabled
Enabled
RW
SC
0
–
16.14
ICS reserved
Reserved
Reserved
RW/0
–
0
16.13
ICS reserved
Reserved
Reserved
RW/0
–
0
16.12
ICS reserved
Reserved
Reserved
RW/0
–
0
16.11
ICS reserved
Reserved
Reserved
RW/0
–
0
–
16.10
PHY Address Bit 4
RO
–
1
16.9
PHY Address Bit 3
RO
–
L
16.8
PHY Address Bit 2
RO
–
L
16.7
PHY Address Bit 1
RO
–
L
–
16.6
PHY Address Bit 0
RO
–
L
16.5
Stream Cipher Test
Mode
Normal operation
Test mode
RW
–
0
16.4
ICS reserved
Read unspecified
Read unspecified
RW/0
–
–
16.3
NRZ/NRZI encoding
NRZ encoding
NRZI encoding
RW
–
1
8
16.2
Transmit invalid codes
Disabled
Enabled
RW
–
0
16.1
ICS reserved
Read unspecified
Read unspecified
RW/0
–
0
16.0
Stream Cipher disable
Stream Cipher enabled
Stream Cipher disabled
RW
–
0
Register
17 - Quick Poll Detailed Status Register
17.15
Data rate
10 Mbps
100 Mbps
RO
–
–
–
17.14
Duplex
Half duplex
Full duplex
RO
–
–
17.13
Auto-Negotiation
Progress Monitor Bit 2
Reference Decode Table
Reference Decode Table
RO
LM
X
0
17.12
Auto-Negotiation
Progress Monitor Bit 1
Reference Decode Table
Reference Decode Table
RO
LM
X
0
Bit
Definition
When Bit = 0
When Bit = 1
Access 2
SF2
Default3
Hex



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