BIT(S)

BIT REF.

DESCRIPTION

13-14

S[0]..S[1]

PLL post-scaler/test mode select bits.

S[1] S[0]

DESCRIPTION

0

0

Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider

drives the LOAD output which, in turn, drives the N2 divider.

0

1

Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider

drives the LOAD output which, in turn, drives the N2 divider.

1

0

Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divder

drives the LOAD output which, in turn, drives the N2 divider.

1

1

AUXEN CLOCK MODE. The AUXCLK bit drives the differential

outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD

output which, in turn, drives the N2 divider.

15

AUX_CLK

When in the AUXEN clock mode, this bit controls the differential outputs.

16

AUX_N1

When in the AUXEN clock mode, this bit controls the N1 output (and

consequently the N2 output according to its programming). When not in

the AUXEN clock mode, this bit, if set to one, will override the N1 divider

modulus and output the VCO frequency divided by two [F(PLL)/2] at the

LOAD output.



17-24

N2[0]..N2[7]

 Sets the modulus of the N2 divider. The input of the N2 divider is the

28

N2[8]

 output of the N1 divider in all clock modes except AUXEN.

25-27

V[0]..V[2]

Sets the gain of VCO according to this table.

V[2]

V[1]

V[0]

VCO GAIN

(MHz/VOLT)

100

30

101

45

110

60

111

80

29-30

P[0]..P[1]

Sets the gain of the phase detector according to this table.

P[1]

P[0]

GAIN (uA/radian)

00

0.05

01

0.15

10

0.5

11

1.5

31

RESERVED

Set to zero.

32

P[2]

Phase detector tuning bit. Should normally be set to one.

ICS1562B

12