AMD-766AC datasheet(71/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

PM16: Resume Event Enable Register

IO mapped (base pointer: C3A58); offset: 17-16h. Default: 0000h. Read-write.

For these bits, 1=Enable the specified event to resume the system out C2, C3, or POS.

Reserved

RI_RSM

Reserved

SIT_RSM

RTC_RSM

IRQ_RSM

765

43210

USB_RSM

SLPB_RSM SMBA_RSM HSLV_RSM SNP_RSM

EXT_RSM

PME_RSM

PB_RSM

PB_RSM. Resume on PM00[PWRBTN_STS]=1.

PME_RSM. Resume on PM20[PME_STS]=1.

EXT_RSM. Resume on PM20[EXTSMI_STS]=1.

SNP_RSM. Resume PME0[SNP_STS]=1.

HSLV_RSM. Resume on PME0[HSLV_STS]=1.

SMBA_RSM. Resume on PME0[SMBA_STS]=1.

SLPB_RSM. Resume on PM00[SLPBTN_STS]=1.

USB_RSM. Resume on PM20[USB_RSM_STS]=1.

IRQ_RSM. Resume on assertion of an unmasked IRQ (when INTR to the processor is set). Note: IRQ0, the timer

tick interrupt, may be masked from generating these resume events via C3A50[PITRSM#].

RTC_RSM. Resume on PM00[RTC_STS]=1.

SIT_RSM. Resume on PM20[SIT_STS]=1.

RI_RSM. Resume on PM20[RI_STS]=1.

PM18: Flag Write Register

IO mapped (base pointer: C3A58); offset: 19-18h. Default: 0000h. Read-write.

15:0

FWRDATA

FWRDATA. Flag write data. Writes to this register are routed to the ISA bus with the FLAGWR pin asserted. The

SA and SD ISA bus pins are guaranteed to be valid at least 30 nanoseconds before and 20 nanoseconds after

FLAGWR is asserted. Reads provide the last data written to this register (internally latched). PM18 and PM1A

should not be read in a single cycle; the two registers are required to be read separately. To use the FLAGWR pin,

PMCA is required to be configured as the FLAGWR function.

PM1A: Flag Read Register

IO mapped (base pointer: C3A58); offset: 1B-1Ah. Default: 0000h. Read only.

15:0

FRDDATA

FRDDATA. Flag read data. Reads from this register are routed to the ISA bus with the FLAGRD# pin asserted.

FLAGRD# is asserted with the same timing as IOR# for these cycles. PM18 and PM1A should not be read in a

single cycle; the two registers are required to be read separately. To use the FLAGRD# pin, PMCB is required to be

configured as the FLAGRD# function.

PM1E (PM2F): Software SMI Trigger Register

IO mapped (base pointer: C3A58); offset: 1Eh. Default: 00h. Read-write. This address accesses the same physical

used to set PM28[SWI_STS]).

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