ICS671-03

3.3 VOLT ZERO DELAY, LOW SKEW BUFFER

ZDB AND MULTIPLIER

IDT™ 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER

2

ICS671-03

REV D 051310

Pin Assignment

Output Clock Mode Select Table

Note 1: Outputs are in high impedance state with weak pulldowns.

Note 2: Buffer mode only; not zero delay between input and output.

Pin Descriptions

Note: Outputs have a weak internal pull-down when in tri-state mode.

S2

S1

CLKA1:A4

CLKB1:B4

A & B Source

PLL Status

0

0

Tri-state (note 1)

Tri-state (note 1)

PLL

ON

0

1

Stopped Low

Stopped Low

None

OFF

1

0

Running

Running

CLKIN (note 2)

OFF

1

1

Running

Running

PLL

ON

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

CLKIN

Input

Clock Input (5 V tolerant).

2, 3, 14, 15

CLKA1:A4

Output

Clock Outputs A1:A4. See above table. Outputs have weak pulldown resistors.

4, 13

VDD

Power

Power supply. Connect both pins to 3.3 V.

5, 12

GND

Power

Connect to ground.

6, 7, 10, 11

CLKB1:B4

Output

Clock Outputs B1:B4. See above table. Outputs have weak pulldown resistors.

8

S2

Input

Select input 2. See table above. Internal pull-up.

9

S1

Input

Select input 1. See table above. Internal pull-up.

16

FBIN

Input

Feedback Input. Connect to any output under normal operation (5 V tolerant).