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ADIS16120/PCB bảng dữ liệu(PDF) 8 Page - Analog Devices

tên linh kiện ADIS16120/PCB
Giải thích chi tiết về linh kiện  Low Noise, Angular Rate Sensor
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ADIS16120/PCB bảng dữ liệu(HTML) 8 Page - Analog Devices

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ADIS16120
Rev. A | Page 8 of 12
THEORY OF OPERATION
The base sensor in the ADIS16120 operates on the principle of
a resonator gyroscope. Two polysilicon sensing structures each
contain a dither frame that is electrostatically driven to reso-
nance. This produces the necessary velocity element that creates
a Coriolis force during angular motion. At the two outer extremes
of each frame, orthogonal to the dither motion, are movable
fingers that are placed between fixed fingers to form a capaci-
tive pickoff structure that senses Coriolis acceleration. The
resulting signal is fed to a series of gain and demodulation
stages that produce the representative rate signal output. One
advantage of the core dual-sensor design approach is that it
provides improved rejection of external g-forces and vibration.
The ADIS16120 signal conditioning circuit provides an
optimized filtering network that controls the resonators
influence on noise while supporting a nominal bandwidth
of 320 Hz. Another feature that helps reduce sensitivity to
power supply noise is the integration of approximately 1.8 μF
of decoupling capacitance inside the ADIS16120.
The offset and sensitivity performance is factory calibrated and
the internal reference voltage used in this calibration process is
offered for external use. A temperature sensor is also provided
for system level use, where appropriate.
SETTING THE BANDWIDTH
An important trade-off in angular rate measurement applica-
tions is the one between total system noise and bandwidth. The
ADIS16120 offers the flexibility to optimize this trade-off at the
system level. The signal processing circuit of the ADIS16120
provides a three-pole, low-pass filter, as shown in Figure 14.
LPF
180kΩ
180kΩ
820pF
FILTER
RATEOUT
OUTPUT
BUFFER
F1 = 400Hz
±35%
LPF
F2 = 1kHz
±10%
F3 = 1kHz
±10%
Figure 14. Simplified Filtering Network
The bandwidth of the third stage can be reduced by installing a
single capacitor across the RATEOUT and FILTER pins. Figure 15
provides a relationship for selecting the appropriate capacitor
value and Table 5 provides bandwidth estimates for standard
capacitor values.
The initial bandwidth of the ADIS16120 is dominated by the first
stage and is dependent on the process variation of the base sensor.
By reducing the bandwidth of the third filter stage, the influence of
the first stage is reduced, and tighter bandwidth tolerances can be
achieved.
1000
100
10
1
0.1
0.01
0.001
100
100M
10M
1M
100k
10k
1k
CAPACITANCE (pF)
Figure 15. Bandwidth vs. Capacitance
Table 5. Nominal Bandwidth for Standard Capacitor Values
C (pF)
BW (Hz)
C (pF)
BW (Hz)
1000
267.3
10,000
78.4
1200
256.2
12,000
67.1
1500
244.1
15,000
55.2
1800
225.5
18,000
46.4
2200
211.9
22,000
38.8
2700
192.3
27,000
31.8
3300
173.2
33,000
26.2
3900
156.4
39,000
22.2
4300
148.9
43,000
20.2
4700
140.4
47,000
18.5
5100
132.9
51,000
17.1
5600
124.5
56,000
15.6
6200
115.6
62,000
14.1
7500
99.0
75,000
11.7
8200
92.7
82,000
10.7
9100
85.5
91,000
9.6
SELF-TEST FUNCTION
The ADIS16120 provides a self-test function that exercises the
mechanical structure of the sensor. To use this function, Pin 1 to
Pin 7 and Pin 9 must be tied together and driven to a high logic
state to activate this function. A continuous self-test does not
damage the device.



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