CDCU2A877ZQLR datasheet(6/14 Pages) TI

6 / 14 page

www.ti.com

ELECTRICAL CHARACTERISTICS

TIMING REQUIREMENTS

CDCU2A877

SCAS827 – AUGUST 2006

over recommended operating free-air temperature range

AVDD,

PARAMETERLow-level output voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDDG

VIK

Input (cl inputs)

II = –18 mA

1.7 V

–1.2

IOH = -100 A

1.7 V to

VDDQ

1.9 V

– 0.2

VOH

High-level output voltage

IOH = –18 mA

1.7 V

1.1

IOL = 100 µA

0.1

VOL

Low-level output voltage

IOL = 18 mA

1.7 V

0.6

IO(DL)

Low-level output current, disabled

VO(DL) = 100 mV, OE = L

1.7 V

100

µA

VOD

Differential output voltage(1)

1.7 V

0.6

CK, CK

1.9 V

±250

Input current

µA

OE, OS, FBIN, FBIN

1.9 V

±10

IDD(LD) Supply current, static (IDDQ + IADD)

CK and CK = L

1.9 V

500

µA

CK and CK = 410 MHz,

All outputs are open

1.9 V

300

(not connected to a PCB)

Supply current, dynamic ( IDDQ + IADD) (see (2)

IDD

for CPD calculation)

All outputs are loaded with 2 pF

and 120-

Ω termination resistor,

1.9 V

325

CK and CK = 410 MHz

CK, CK

VI = VDD or GND

1.8 V

Input capacitance

FBIN, FBIN

VI = VDD or GND

1.8 V

CK, CK

VI = VDD or GND

1.8 V

0.25

Change in input

CI(∆)

current

FBIN, FBIN

VI = VDD or GND

1.8 V

0.25

(1)

VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 4 for a definition.

(2)

Total IDD = IDDQ + IADD = fCK× CPD× VDDQ, solving for CPD = (IDDQ + IADD)/(fCK × VDDQ) where fCK is the input frequency, VDDQ is the

power supply, and CPD is the power dissipation capacitance.

over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fCK

Clock frequency (operating)(1)(2)

AVDD, VDD = 1.8 V ±0.1 V

125

410

MHz

fCK

Clock frequency (application)(1)(3)

AVDD, VDD = 1.8 V ±0.1 V

160

410

MHz

tDC

Duty cycle, input clock

AVDD, VDD = 1.8 V ±0.1 V

40%

60%

Stabilization time(4)

AVDD, VDD = 1.8 V ±0.1 V

µs

(1)

The PLL must be able to handle spread spectrum induced skew.

(2)

Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other

timing parameters (used for low speed system debug).

(3)

Application clock frequency indicates a range over which the PLL must meet all timing parameters.

(4)

Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal,

within the value specified by the static phase offset t(φ), after power up. During normal operation, the stabilization time is also the time

required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic

low state, enter the power-down mode, and later return to active operation. CK and CK may be left floating after they have been driven

low for one complete clock cycle.

Submit Documentation Feedback

CDCU2A877ZQLR bảng dữ liệu(PDF) 6 Page - Texas Instruments

CDCU2A877ZQLR bảng dữ liệu(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

bảng dữ liệu tải về

Link URL