FXPS7115D4 datasheet(24/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

3. When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the

CRC check result.

4. If the shift register contains all zeros, the CRC is correct.

5. If the shift register contains a value other than zero, the CRC is incorrect.

The CRC polynomial and seed are shown in Table 29.

SPICRCSEED[3:0]

Default Polynomial

Default non-direct Seed

0000

x8+ x5+ x3+ x2+ x + 1

1111 1111

non-zero

x8+ x5+ x3+ x2+ x + 1

1111 SPICRCSEED[3:0]

Table 29. SPI Command Message CRC

7.5.4.1.2 Response error checking

The device calculates a CRC on the entire 32 bits of each response. Message data is entered into the CRC

calculator MSB first, consistent with the transmission order of the message.

The CRC encoding procedure is as follows:

1. A seed value is preset into the LSB of the shift register.

2. Using a serial CRC calculation method, the transmitter rotates the transmitted message and CRC into the

LSB of the shift register (MSB first).

3. Following the transmitted message, the transmitter feeds 8 zeros into the shift register, to match the length

of the CRC.

4. When the last zero is fed into the input adder, the shift register contains the CRC.

5. The CRC is transmitted.

The CRC polynomial and seed are shown in Table 30.

SPICRCSEED[3:0]

Default Polynomial

Default non-direct Seed

0000

x8+ x5+ x3+ x2+ x + 1

1111 1111

nonzero

x8+ x5+ x3+ x2+ x + 1

1111 SPICRCSEED[3:0]

Table 30. SPI Response Message CRC

7.5.5 Exception handling

After POR, there a supply error flag is set. Expected initial responses with first 4 commands are shown in

Table 31.

Command

Response

Command 1 (DEVSTAT READ)

Ignore response 1

Command 2 (DEVSTAT READ)

Ignore response 2

Command 3 (DEVSTAT READ)

Ignore response 3

Command 4 (ANY USER COMMAND)

Response 4 - 0X6080XXXX[1]

Table 31. Expected initial responses after tPOR_DataValid post POR

[1]

Response 4 is 0x6080XXXX after tPOR_DataValid wait time from POR. Otherwise only after tPOR_I2C/POR_SPI wait time from POR, response would be 0x6081

XXXX due to DEVINIT bit still set to 1.

Before soft reset, write SOURCEID_0 in address 1Ah with a non-zero value. Address 1Ah is read back to check

soft reset sanity.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.1 — 7 June 2023

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