2

AT90SC9618RT

6516AS–SMIC–28Jun05

Instruction

Decoder

Program

Memory

Instruction

Register

Access

Control

General

Purpose

Registers

X

Y

Z

Status

Register

RAM

Data Memory

Interrupt

Unit

ISO 7816

I/O Port 0

Timer

Control

Lines

ALU

EEPROM

User Memory

OTP

PC

Secure

Control

GND

CLK

Access

Control

IN/OUT0

Data Bus

8-bit

RNG

16

16

16

8

88

DES

DPA Counter

measures

Reset

Circuit

RST

ISO 7816

Controller

CRC and

Checksum

Accelerator

Description

The AT90SC9618RT is a low-power, high-performance, 8/16-bit microcontroller with ROM program memory, EEPROM

data memory and is based on the secureAVR enhanced RISC architecture. By executing powerful instructions in a single

clock cycle, the AT90SC9618RT achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32 gen-

eral purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one

single instruction executed in one clock cycle.

The AT90SC9618RT uses the secureAVR that allows the linear addressing of up to 8M bytes of code and up to 16M bytes

of data as well as a number of new functional and security features.

The AT90SC9618RT includes 18K bytes of Atmel’s high density, non volatile memory.

Additional security features include power and frequency protection logic, logical scrambling on program data and

addresses, Power Analysis countermeasures and memory accesses controlled by a supervisor mode.

Figure 1 shows the AT90SC9618RT secureAVR Enhanced RISC Architecture.