REV. A

ADP3158/ADP3178

–6–

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VID0

VID1

VID2

VID3

LRFB1

LRDRV1

CS–

CS+

GND

DRVH

DRVL

VCC

LRFB2

LRDRV2

COMP

CT

FROM CPU

C1

100 F

C15

1 F

C2

100 F

Q2

*

C12

1 F

Q1

*

C3

150pF

10.5k

78.7k

2.7nF

3.3V

C17 C18 C19 C20 C21

1.8V,

2A

R12

4m

L1

1.7 H

Q4

*

Q3

**

C8

1000 F

C9

1000 F

C7

22 F

L2

1 H

VCC CORE

1.30V TO

2.05V

15A

5V

5V STANDBY

12V

D3

MBR052LT1

D2

MBR052LT1

2.5V, 2A

C6

1 F

R4

220

R3

220

C10

1nF

3.3V

ADP3158/

ADP3178

+

+

+

+

+

+

+

+

+

+

+

U1

C2

68pF

C11

68pF

R2

10k

R11

10k

1000 F

5

24m

(EACH)

Figure 3. 15 A Pentium III Application Circuit

The linear regulator controllers have been designed so that they

remain active even when the switching controller is in UVLO mode

to ensure that the output voltages of the linear regulators will track

the 3.3 V supply as required by Intel design specifications. By

diode ORing the VCC input of the IC to the 5 VSB and 12 V

supplies as shown in Figure 3, the switching output will be disabled

in standby mode, but the linear regulators will begin conducting

once VCC rises above about 1 V. During start-up the linear out-

puts will track the 3.3 V supply up until they reach their respective

regulation points, regardless of the state of the 12 V supply. Once

the 12 V supply has exceeded the 5 VSB supply by more than a

diode drop, the controller IC will track the 12 V supply. Once the

12 V supply has risen above the UVLO value, the switching regula-

tor will begin its start-up sequence.

Table I. Output Voltage vs. VID Code

VID3

VID2

VID1

VID0

1

1

1

1

1.30 V

1

1

1

0

1.35 V

1

1

0

1

1.40 V

1

1

0

0

1.45 V

1

0

1

1

1.50 V

1

0

1

0

1.55 V

1

0

0

1

1.60 V

1

0

0

0

1.65 V

0

1

1

1

1.70 V

0

1

1

0

1.75 V

0

1

0

1

1.80 V

0

1

0

0

1.85 V

0

0

1

1

1.90 V

0

0

1

0

1.95 V

0

0

0

1

2.00 V

0

0

0

0

2.05 V

APPLICATION INFORMATION

Specifications for a Design Example

The design parameters for a typical 750 MHz Pentium III appli-

cation (shown in Figure 3) are as follows:

Static tolerance of the supply voltage for the processor core

(

∆V

Transient tolerance (for less than 2

µs) of the supply voltage

for the processor core when the load changes between the

minimum and maximum values with a di/dt of 20 A/

µs

(

∆V

Input current di/dt when the load changes between the mini-

mum and maximum values < 0.1 A/

µs.

The above requirements correspond to Intel’s published power

supply requirements based on VRM 8.4 guidelines.