ADM1176-2ARMZ-R7 datasheet(15/24 Pages) AD

15 / 24 page

ADM1176

Rev. 0 | Page 15 of 24

When the initial timing cycle terminates, the device is ready to

start a hot swap operation (assuming ON pin is asserted). In the

example shown in Figure 30, the ON pin is asserted at the same

time that VCC is applied, so the hot swap operation starts

immediately after Time Point (4). At this point, the FET gate is

charged up with a 12 μA current source.

At Time Point (5), the threshold voltage of the FET is reached,

and the load current begins to flow. The FET is controlled to

keep the sense voltage at 100 mV (this corresponds to a

maximum load current level defined by the value of RSENSE).

At Time Point (6), VGATE and VOUT have reached their full

potential, and the load current has settled to its nominal level.

Figure 31 illustrates the situation where the ON pin is asserted

after VCC is applied.

VVCC

(1)

INITIAL TIMING

CYCLE

(2)

(3) (4) (5)

(6)

VON

VTIMER

VGATE

VSENSE

VOUT

Figure 30. Startup (ON Asserts as Power Is Applied)

INITIAL TIMING

CYCLE

VVCC

VON

VTIMER

VGATE

VSENSE

VOUT

(1)

(2)

(3) (4)

(5)(6)

(7)

Figure 31. Startup (ON Asserts After Power Is Applied)

HOT SWAP RETRY ON THE ADM1176-1

With the ADM1176-1, the device turns off the FET after an

overcurrent fault and then uses the TIMER pin to time a delay

before automatically retrying to hot swap.

As with all ADM1176 devices, on overcurrent fault is timed by

charging the TIMER cap with a 60 μA pull-up current. When

the TIMER pin reaches 1.3 V, the fault current limit time has

been reached, and the GATE pin is pulled down. On the

ADM1176-1, the TIMER pin is then pulled down with a 2 μA

current sink. When the TIMER pin reaches 0.2 V, it automati-

cally restarts the hot swap operation.

The cool-down period is related to CTIMER by Equation 8.

tCOOL ≈ 550 × CTIMER ms/μF

(8)

Thus, the retry duty cycle is given by Equation 9.

tFAULT/(tCOOL + tFAULT ) × 100% = 3.8%

(9)

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