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MCF5484 bảng dữ liệu(PDF) 21 Page - Freescale Semiconductor, Inc |
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MCF5484 bảng dữ liệu(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 28 page ![]() General Timing Specifications MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 Freescale Semiconductor 21 12 General Timing Specifications Table 19 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts. 13 I2C Input/Output Timing Specifications Table 20 lists specifications for the I2C input timing parameters shown in Figure 19. Table 21 lists specifications for the I2C output timing parameters shown in Figure 19. Table 19. General AC Timing Specifications Name Characteristic Min Max Unit G1 CLKIN high to signal output valid — 2 PSTCLK G2 CLKIN high to signal invalid (output hold) 0 — ns G3 Signal input pulse width 2 — PSTCLK Table 20. I2C Input Timing Specifications between SCL and SDA Num Characteristic Min Max Units I1 Start condition hold time 2 — Bus clocks I2 Clock low period 8 — Bus clocks I3 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — 1 mS I4 Data hold time 0 — ns I5 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 1 mS I6 Clock high time 4 — Bus clocks I7 Data setup time 0 — ns I8 Start condition setup time (for repeated start condition only) 2 — Bus clocks I9 Stop condition setup time 2 — Bus clocks Table 21. I2C Output Timing Specifications between SCL and SDA Num Characteristic Min Max Units I11 Start condition hold time 6 — Bus clocks I2 1 Clock low period 10 — Bus clocks I3 2 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — — µS I4 1 Data hold time 7 — Bus clocks I5 3 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 3 ns I6 1 Clock high time 10 — Bus clocks I7 1 Data setup time 2 — Bus clocks I8 1 Start condition setup time (for repeated start condition only) 20 — Bus clocks I9 1 Stop condition setup time 10 — Bus clocks |
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