ICS9LPRS525

IDT®

PC MAIN CLOCK

1484F—08/10/12

56-pin CK505 for Intel Systems

1

DATASHEET

Pin Configuration

Recommended Application:

56-pin CK505 compatible clock, w/fully integrated Vreg and series

resistors on differential outputs

Output Features:

•

2 - CPU differential low power push-pull pairs

•

7 - SRC differential push-pull pairs

•

1 - CPU/SRC selectable differential low power push-pull pair

•

1 - SRC/DOT selectable differential low power push-pull pair

•

1 - SRC/SE selectable differential push-pull pair/Single-ended

outputs

•

5 - PCI, 33MHz

•

1 - USB, 48MHz

•

1 - REF, 14.318MHz

Key Specifications:

•

CPU outputs cycle-cycle jitter <85ps

•

SRC output cycle-cycle jitter <85ps

•

PCI outputs cycle-cycle jitter <250ps

•

+/- 100ppm frequency accuracy on all outputs

•

SRC outputs meet PCIe Gen2 when sourced from PLL3

Features/Benefits:

•

Supports spread spectrum modulation, 0 to -0.5% down

spread

•

Supports CPU clks up to 400MHz

•

Uses external 14.318MHz crystal, external crystal load

caps are required for frequency tuning

Table 1: CPU Frequency Select Table

FSLC

2

B0b7

FSLB

1

B0b6

FSLA

1

B0b5

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

USB

MHz

DOT

MHz

0

0

0

266.66

0

0

1

133.33

0

1

0

200.00

0

1

1

166.66

1

0

0

333.33

1

0

1

100.00

1

1

0

400.00

11

1

1. FS

LA and FSLB are low-threshold inputs.Pleas e see VIL_FS and VIH_FS specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FS

LC is a three-level input. Please s ee the VIL_FS and VIH_FS

specifications in the Input/Supply/Common Output Parameters Table for correct values.

Reserved

96.00

100.00

33.33 14.318 48.00

PCI0/CR#_A 1

56 SCLK

VDDPCI 2

55 SDATA

PCI1/CR#_B 3

54 REF0/FSLC/TEST_SEL

PCI2/TME 4

53 VDDREF

PCI3/CFG0 5

52 X1

PCI4/SRC5_EN 6

51 X2

PCI_F5/ITP_EN 7

50 GNDREF

GNDPCI 8

49 FSLB/TEST_MODE

VDD48 9

48 CK_PWRGD/PD#

USB_48MHz/FSLA 10

47 VDDCPU

GND4811

46CPUT0_LRS

VDD96IO 12

45 CPUC0_LRS

DOTT_96_LRS/SRCT0_LRS 13

44 GNDCPU

DOTC_96_LRS/SRCC0_LRS 14

43 CPUT1_F_LRS

GND 15

42 CPUC1_F_LRS

VDD 16

41 VDDCPUIO

SRCT1_LRS/SE1 17

40 NC

SRCC1_LRS/SE2 18

39 CPUT2_ITP_LRS/SRCT8_LRS

GND 19

38 CPUC2_ITP_LRS/SRCC8_LRS

VDDPLL3IO 20

37 VDDSRCIO

SRCT2_LRS/SATAT_LRS 21

36 SRCT7_LRS/CR#_F

SRCC2_LRS/SATAC_LRS 22

35 SRCC7_LRS/CR#_E

GNDSRC 23

34 GNDSRC

SRCT3_LRS/CR#_C 24

33 SRCT6_LRS

SRCC3_LRS/CR#_D 25

32 SRCC6_LRS

VDDSRCIO 26

31 VDDSRC

SRCT4_LRS 27

30 PCI_STOP#/SRCT5_LRS

SRCC4_LRS 28

29 CPU_STOP#/SRCC5_LRS

56-TSSOP