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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ICS9LPRS511 bảng dữ liệu(PDF) 12 Page - Renesas Technology Corp |
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ICS9LPRS511 bảng dữ liệu(HTML) 12 Page - Renesas Technology Corp |
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12 / 20 page  12 Integrated Circuit Systems, Inc. ICS9LPRS511 Advance Information 1137—09/05/08 I2C Table: Output Control Register Byte 20 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 Reserved Reserved RW 0 Bit 6 Reserved Reserved RW 0 Bit 5 Reserved Reserved RW 0 Bit 4 Reserved Reserved RW 0 Bit 3 PCIEX PLL TBEN PCIEX PLL Turbo Enable RW 0 Bit 2 CPU PLL TBEN CPU PLL Turbo Enable RW 0 Bit 1 Reserved Reserved RW 0 Bit 0 RESET Sync Reset Synchronization upon Reset (Byte 21) RW 0 Disable - - - - 01 -- - - Enable Enable - Disable Enable Disable - I2C Table: Synchronization Control Register Byte 21 Name Control Function Type PWD A/B PWD C/D/E/H PWD J Bit 7 PCIEX Source PCIEX Source RW 0 1 0 Bit 6 SATA Source SATA Source RW 1 1 1 Bit 5 Reserved Reserved RW 1 1 1 Bit 4 Reserved Reserved RW 1 1 1 Bit 3 Reserved Reserved RW 1 1 1 Bit 2 Reserved Reserved RW 1 1 1 Bit 1 Reserved Reserved RW 1 1 1 Bit 0 Reserved Reserved RW 1 1 1 - 01 - -- - - CPU PLL PCIEX PLL PCIEX PLL - Fixed PLL - - - - - I2C Table: DOC pin control register Byte 22 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 PCIEX PCIEX PLL DOC0 pin control RW 1 Bit 6 CPU CPU PLL DOC0 pin control RW 0 Bit 5 Reserved Reserved RW 0 Bit 4 Reserved Reserved RW 0 Bit 3 Reserved Reserved RW 0 Bit 2 Reserved Reserved RW 0 Bit 1 Reserved Reserved RW 1 Bit 0 Reserved Reserved RW 1 I2C Table: CPU PLL DOC 1 N programming Register (DOC0 = 1) Byte 23 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 N Div10 RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW X Bit 4 N Div7 RW X Bit 3 N Div6 RW X Bit 2 N Div5 RW X Bit 1 N Div4 RW X Bit 0 N Div3 RW X Bytes 24 and 25 are reserved I2C Table: PCIEX PLL DOC 1 N programming Register (DOC0 = 1) Byte 26 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 N Div10 RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW X Bit 4 N Div7 RW X Bit 3 N Div6 RW X Bit 2 N Div5 RW X Bit 1 N Div4 RW X Bit 0 N Div3 RW X 01 N Divider Programming Byte26 bit(7:0) and Byte15 bit(7:6) The decimal representation of M and N Divider in Byte 15 and 26 will configure the PCIEX PLL VCO frequency. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) 01 N Divider Programming Byte23 bit(7:0) and Byte11 bit(7:6) The decimal representation of M and N Divider in Byte 11 and 23 will configure the CPU PLL VCO frequency. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) -- -- -- -- -- -- 01 Enabled Disabled Enabled Disabled |
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