ADIS16201SLASHPCB datasheet(23/32 Pages) AD

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Data Sheet

ADIS16201

Rev. C | Page 23 of 32

ALM_CTRL Register Definition

Address

Default1

Format

Access

0x29, 0x28

0x0000

N/A

R/W

1 Default is valid only until the first register write cycle.

The ALM_CTRL register contains the alarm control variables.

Table 23. ALM_CTRL Bit Designations

Bit

Value

Description

Rate of change (ROC) enable for Alarm 2.

1: ROC is active.

0: ROC is inactive.

14:12

Alarm 2 source selection.

000

Alarm disable.

001

Alarm source: power supply output.

010

Alarm source: X-acceleration output.

011

Alarm source: Y-acceleration output.

100

Alarm source: auxiliary ADC output.

101

Alarm source: temperature sensor output.

110

Alarm source: X-inclination output.

111

Alarm source: Y-inclination output.

Rate of change (ROC) enable for Alarm 1.

1: ROC is active.

0: ROC is inactive.

10:8

Alarm 1 source selection.

000

Alarm disable.

001

Alarm source: power supply output.

010

Alarm source: X-acceleration output.

011

Alarm source: Y-acceleration output.

100

Alarm source: auxiliary ADC output.

101

Alarm source: temperature sensor output.

110

Alarm source: X-inclination output.

111

Alarm source: Y-inclination output.

7:3

Not used.

Alarm output enable.

1: Alarm output enabled.

0: Alarm output disabled.

Alarm output polarity.

1: Active high.

0: Active low.

Alarm output line select.

1: DIO1.

0: DIO0.

SAMPLE PERIOD CONTROL

The seven output data variables within the ADIS16201 are

sampled and updated at a rate based upon the SMPL_PRD

control register. The sample period can be precisely controlled

over more than a 3-decade range using a time base with two

settings and a 7-bit binary count. The use of a time base that

varies with a ratio of 1:31 allows for a more optimal resolution

in the sample period than a straight binary counter. This is

reflected in Figure 36, where the frequency is presented on a

logarithmic scale. The choice of the two time base settings

results in making the sample period setting more linear vs. the

logarithmic frequency scale.

Note that the sample period given is defined as the cumulative

time required to sample, process, and update all seven data output

variables. The seven data output variables are sampled as a

group and in unison with one another. Whatever update rate is

selected for one signal, all seven output data variables are updated

at the same rate whether they are monitored via the SPI or not.

For a sample period setting of less than 1098.9 μs (SMPL_RATE ≤

0x07), the overall power dissipation in the part rises by approxi-

mately 300%. The default setting for the SMPL_RATE register is

0x04 at initial power-up, thus allowing for the maximum SPI

clock rate of 2.5 MHz.

256

10k

FREQUENCY (Hz)

192

128

100

Figure 36. SMPL_PRD Values vs. Sample Frequency

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