PID9q-604e Hardware Specifications

21

PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE

Table 11. PLL Configuration

PLL_CFG

[0Ð3]

CPU/

SYSCLK

Ratio

VCO

Multiplier

CPU Frequency in MHz

(VCO Frequency in MHz)

Bin

Dec

Bus

25

MHz

Bus

33.3

MHz

Bus

40

MHz

Bus

50

MHz

Bus

60

MHz

Bus

66.6

MHz

Bus

83.3

MHz

Bus

100

MHz

0000

0

1:1

x2

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

0001

1

1:1

x8

Ñ

Ñ

40

(320)

50

(400)

60

(480)

66

(533)

83.3

(666)

Ñ

1100

12

1.5:1

x2

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

0100

4

2:1

x2

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

200

(400)

0110

6

2.5:1

x2

Ñ

Ñ

Ñ

Ñ

Ñ

Ñ

208

(416)

250

(500)

1000

8

3:1

x2

Ñ

Ñ

Ñ

Ñ

Ñ

200

(400)

250

(500)

300

(600)

1110

14

3.5:1

x2

Ñ

Ñ

Ñ

Ñ

210

(420)

233

(466)

292

(584)

350

(700)

1010

10

4:1

x2

Ñ

Ñ

Ñ

200

(400)

240

(480)

266

(532)

333

(666)

Ñ

0111

7

4.5:1

x2

Ñ

Ñ

Ñ

225

(450)

270

(540)

300

(600)

ÑÑ

1011

11

5:1

x2

Ñ

Ñ

200

(400)

250

(500)

300

(600)

333

(666)

ÑÑ

1001

9

5.5:1

x2

Ñ

Ñ

220

(440)

275

(550)

330

(660)

ÑÑÑ

1101

13

6:1

x2

Ñ

200

(400)

240

(480)

300

(600)

Ñ

ÑÑÑ

0101

5

6.5:1

x2

Ñ

216

(433)

260

(520)

325

(650)

Ñ

ÑÑÑ

0010

2

7:1

x2

Ñ

233

(466)

280

(560)

350

(700)

Ñ

ÑÑÑ

0011

3

PLL bypass

1111

15

Clock off

Notes:

1. Some PLL conÞgurations may select bus, CPU, or VCO frequencies which are not supported; see

Section 1.4.2.2, ÒInput AC SpeciÞcations,Ó for valid SYSCLK and VCO frequencies.

2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is

disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.

Note: The AC timing speciÞcations given in this document do not apply in PLL-bypass mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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