A121 Pulsed Coherent Radar (PCR)

Datasheet v1.0

Page 19 of 29

2023-03-30

© 2023 Copyright by Acconeer

6.3 Sensor startup

The power-up and power-down sequences are shown in Figure 6.4.

Figure 6.4. Power-up and power-down sequences.

The power supplies VRX, VTX, VDIG and VIO can be turned on and off in any order. ENABLE

should be turned on after or simultaneously with VDIG and VIO, whichever is turned on last. The

A121 should however not be considered as in state “ON” until all supply voltage levels are stable and

ENABLE is high. The time constant t1 in Figure 6.4 denotes this time. The actual value of t1 depends

on the power supply and the decoupling capacitors used. Any I/O must be held at 0 V during time t1.

After power-up is complete, the sensor is ready for SPI communication and can be loaded with a

program. Note that time between ENABLE high until start of SPI communication is dependent on

XTAL startup time, typically 2 ms.

Up until the point where the sensor’s program is started, the INTERRUPT is in a high impedance

state. After the sensor’s program has started, the INTERRUPT is configured as a push-pull CMOS

output.

The power down sequence is initiated by setting ENABLE low. After that, all supplies can be turned

off. Any I/O inputs on A121 must be set to 0 V before or simultaneously with VIO going low to avoid

forward-biasing the internal ESD protection diodes.

6.4 Layout Recommendations

The sensor antennas are of a folded dipole type, with its main ground reference being the internal

package ground plane, extending below the whole area of the sensor. To further enhance the

directivity of the sensor, the package ground plane should be extended by soldering all GND pads to

the PCB top layer ground. In terms of regulatory compliance, any openings in the ground plane inside

the A121 footprint must be significantly smaller than the wavelength (5 mm in free space) to

effectively shield off any disturbance.

It is important to consider PCB layout for optimal RLG performance. PCB layout guidelines can be

found in the document “Hardware and physical integration guideline”.

Time

VRX

VTX

VDIG

VIO

ENABLE

t1

t2