AD12401SLASHKIT datasheet(18/28 Pages) AD

18 / 28 page

AD12401

Rev. A | Page 18 of 28

THEORY OF OPERATION

The AD12401 uses two high speed, 12-bit ADCs in a time-

interleaved configuration to double the sample rate, while

maintaining a high level of dynamic range performance. The

digital output of each ADC channel is calibrated using a

proprietary digital postprocessing technique, Advanced Filter

Bank (AFB). AFB is implemented using a state-of-the-art field

programmable gate array (FPGA) and provides a wide

bandwidth and wide temperature match for any gain, phase,

and clock timing errors between each ADC channel.

TIME-INTERLEAVING ADCS

When two ADCs are time-interleaved, gain and/or phase

mismatches between each channel produce an image spur at

fS/2 − fAIN and an offset spur, as shown in Figure 19. These

mismatches can be the result of any combination of device

tolerance, temperature, and frequency deviations.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

100

120

140

160

180

200

FREQUENCY (MHz)

IMAGE SPUR

OFFSET SPUR

Figure 19. Image Spur due to Mismatches Between Two Interleaved ADCs

(No AFB Digital Postprocessing)

Figure 20 shows the performance of a similar converter with

on-board AFB postprocessing implemented. The –44 dBFS

image spur has been reduced to –77 dBFS and, as a result, the

dynamic range of this time-interleaved ADC is no longer

limited by the channel matching.

100

120

140

160

180

200

FREQUENCY (MHz)

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

IMAGE SPUR

OFFSET SPUR

Figure 20. AD12401 with AFB Digital Postprocessing

The relationship between image spur and channel mismatches

is captured in Table 10 for specific conditions.

Table 10. Image Spur vs. Channel Mismatch

Gain Error (%)

Aperture Delay Error (ps)

Image Spur (dBc)

–40

0.25

2.7

–54

0.2

1.1

–62

0.025

0.5

–70

For a more detailed description of time-interleaving in ADCs and a

design example using the AD12401, see Advanced Digital Post-

Processing Techniques Enhance Performance in Time-Interleaved

ADC Systems, which was published in the August, 2003 edition of

the Analog Dialogue (www.analog.com/analogDialogue).

ANALOG INPUT

The AD12401 analog input is ac-coupled using a proprietary

transformer front-end circuit that provides 1 dB of gain flatness

over the first Nyquist zone and a −3 dB bandwidth of 480 MHz.

This front-end circuit provides a VSWR of 1.5 (50 Ω) over the

first Nyquist zone, and the typical full-scale input is 3.2 V p-p.

The Mini-Circuits® HELA-10 amplifier module can be used to

drive the input at these power levels.

CLOCK INPUT

The AD12401 requires a 400 MSPS ENCODE that is divided by 2

and distributed to each ADC channel, 180° out of phase from

each other. Internal ac-coupling and bias networks provide the

framework for flexible clock input requirements that include

single-ended sine wave, single-ended PECL, and differential

PECL. While the AD12401 is tested and calibrated using a

single-ended sine wave, properly designed PECL circuits that

provide fast slew rates (>1 V/ns) and minimize ringing result in

comparable dynamic range performance.

Aperture jitter and harmonic content are two major factors to

consider when designing the input clock circuit for the AD12401.

The relationship between aperture jitter and SNR can be

characterized using the following equation. The equation

assumes a full-scale, single-tone input signal.

SNR =

()

⎥

⎦

⎤

⎢

⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

−

log

NOISErms

JRMS

where:

fA = input frequency.

tJRMS = aperture jitter.

N = ADC resolution (bits).

ε = ADCDNL (LSB).

VNOISErms = ADC input noise (LSB rms).

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