AD9411SLASHPCB datasheet(9/28 Pages) AD

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AD9411

Rev. A | Page 9 of 28

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Function

Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential;

GND sets FS = 1.536 V p-p differential.

2, 42–46,49–52

DNC

Do Not Connect.

3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31,

32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100

AGND

Analog Ground. AGND and DRGND should be tied together to a common

ground plane.

5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34,

39, 40, 88, 89, 90, 94, 95, 98, 99

AVDD

3.3 V Analog Supply.

Data Format Select. GND = binary; AVDD = twos complement.

LVDSBIAS

Set Pin for LVDS Output Current. Place a 3.74 kΩ resistor terminated to

ground.

SENSE

Reference Mode Select Pin. Float for internal reference operation.

VREF

1.235 V Reference Input/Output. Function depends on SENSE.

VIN+

Analog Input. True.

VIN–

Analog Input. Complement.

CLK+

Clock Input. True (LVPECL levels).

CLK–

Clock Input. Complement (LVPECL levels).

47, 54, 62, 75, 83

DRVDD

3.3 V Digital Output Supply (3.0 V to 3.6 V).

48, 53, 61, 67, 74, 82

DRGND

Digital Output Ground. AGND and DRGND should be tied together to a

common ground plane.

D0+

D0 True Output Bit.

D1–

D1 Complement Output Bit.

D1+

D1 True Output Bit.

D2–

D2 Complement Output Bit.

D2+

D2 True Output Bit.

DCO–

Data Clock Output. Complement.

DCO+

Data Clock Output. True.

D3–

D3 Complement Output Bit.

D3+

D3 True Output Bit.

D4–

D4 Complement Output Bit.

D4+

D4 True Output Bit.

D5–

D5 Complement Output Bit.

D5+

D5 True Output Bit.

D6–

D6 Complement Output Bit.

D6+

D6 True Output Bit.

D7–

D7 Complement Output Bit.

D7+

D7 True Output Bit.

D8–

D8 Complement Output Bit.

D8+

D8 True Output Bit.

D9–

D9 Complement Output Bit.

D9+

D9 True Output Bit.

OR–

Overrange Complement Output Bit.

OR+

Overrange True Output Bit.

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