DSP56004ROM datasheet(41/82 Pages) NXP

tên linh kiện	DSP56004ROM

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Specifications

External Memory Interface (EMI) SRAM Timing

MOTOROLA

DSP56004/D, Rev. 3

2-17

EXTERNAL MEMORY INTERFACE (EMI) SRAM TIMING

(CL = 50 pF + 2 TTL Loads)

Figure 2-12 CAS before RAS Refresh Cycle

Table 2-10

External Memory Interface (EMI) SRAM Timing

No.

Characteristics

Symbol

Expression

50 MHz

66 MHz

81 MHz

Unit

Min Max Min Max Min Max

91 Address Valid and CS

Assertion Pulse Width

tRC, tWC

× T

C – 11 +

× T

—

38.4

—

92 Address Valid to RD or WR

Assertion

tAS

TC + TL – 13

—

5.5

—

93 RD or WR Assertion Pulse

Width

tWP

× T

C – 5 +

× T

35—23—

—

94 RD or WR Deassertation to

RD or WR Assertion

—2

× T

C – 11

—

13.7

—

95 RD or WR Deassertation to

Address not Valid

tWR

TH – 6

4—2—

0.2

—

96 Address Valid to Input Data

Valid

tAA, tAC 3 × TC + TL –15 +

× T

—

28.2

97 RD Assertion to Input Data

Valid

tOE

× T

C – 15 +

× T

—25—15

—

9.7

MRAS

MCAS

Data In

MD0–MD7

AA0266

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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