ISL81601 datasheet(37/54 Pages) RENESAS

37 / 54 page

FN9299 Rev.3.1

Page 37 of 53

May 27, 2021

ISL81601

5. Functional Description

5.9

Frequency Selection

Switching frequency selection is a trade-off between efficiency and component size. Low switching frequency

improves efficiency by reducing MOSFET switching loss. To meet the output ripple and load transient

requirements, operation at a low switching frequency requires larger inductance and output capacitance. The

switching frequency of the ISL81601 is set by a resistor connected from the RT/SYNC pin to GND according to

Equation 1 on page 10.

The frequency setting curve shown in Figure 51 assists in selecting the correct value for RT.

Figure 51. RT vs Switching Frequency fSW

5.10

Phase Lock Loop (PLL)

The ISL81601 integrates a high performance PLL. The PLL ensures the wide range of accurate clock frequency

and phase setting. It also makes the internal clock easily synchronized to an external clock with the frequency

either lower or higher than the internal setting.

As shown in Figure 52, an external compensation network of RPLL, CPLL1, and CPLL2 is needed to connect to the

PLL_COMP pin to ensure PLL stable operation. Renesas recommends choosing 2.7kΩ for RPLL, 10nF for CPLL1,

and 820pF for CPLL2. With the recommended compensation network, the PLL stability is ensured in the full clock

frequency range of 100kHz to 600kHz.

Figure 52. PLL Compensation Network

500

1,000

1,500

2,000

2,500

3,000

050

100

150

200

250

RT (k:)

PLL_COMP

CPLL1

RPLL

CPLL2

ISL81601

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