FN8921 Rev.2.00

Page 3 of 28

Jan 19, 2021

ISL71218M

Overview

1.

Overview

1.1

Ordering Information

1.2

Pin Configuration

ISL71218M

(8 Ld SOIC)

Top View

1.3

Pin Descriptions

Part Number

(Notes 2, 3)

Part

Marking

Temp Range

(°C)

Tape and Reel

(Units)

Package

(RoHS Compliant)

Pkg.

Dwg. #

ISL71218MBZ

71218 MBZ

-55 to +125

-

8 Ld SOIC

M8.15

ISL71218MBZ-T (Note 1)

71218 MBZ

-55 to +125

1k

8 Ld SOIC

M8.15

ISL71218MBZ-T7A (Note 1)

71218 MBZ

-55 to +125

250

8 Ld SOIC

M8.15

ISL71218MEVAL1Z

Evaluation Board

Notes:

1. See TB347 for details about reel specifications.

2. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and

NiPdAu-Ag plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), see the ISL71218M device page. For more information about MSL, see TB363.

Pin Number

Pin Name

Equivalent Circuit

Description

1

OUT_A

Circuit 2

Amplifier A output

2

-IN_A

Circuit 1

Amplifier A inverting input

3

+IN_A

Circuit 1

Amplifier A non-inverting input

4V-

Circuit 1, 2, 3

Negative power supply

5

+IN_B

Circuit 1

Amplifier B non-inverting input

6

-IN_B

Circuit 1

Amplifier B inverting input

7

OUT_B

Circuit 2

Amplifier B output

8V+

Circuit 1, 2, 3

Positive power supply

OUT_A

-IN_A

+IN_A

V-

1

2

3

4

8

7

6

5

V+

OUT_B

-IN_B

+IN_B

+

-

+-

V+

V-

OUT

Circuit 2

Circuit 1

V+

V-

Circuit 3

IN-

V+

V-

IN+

Capacitively

Triggered ESD

Clamp