HC705MC4GRSSLASHD datasheet(112/180 Pages) NXP

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Pulse Width Modulator

MC68HC705MC4 — Rev. 2.0

Pulse Width Modulator

Figure 10-16. PWM Interlock Mechanisms

Writing to the direct address will not activate the interlock mechanism

with the control register. The new value will be updated at the end of the

current PWM cycle if the update bit is clear. The new value will be

updated immediately if the update bit is set.

NOTE:

In either case above (write to interlock or direct addresses), the

additional interlock mechanism that interlocks channel A and channel B

together may preempt the transfer of the new data to the active registers.

See 10.7.2 Operation with the Same PWM Rates for more detail.

PWMx-D

PWMB-I

PWMB-D

PWMA-D

PWMB-I

PWMA-I

CTL-B

CTL-A

PWMA-I

CTL-A

CTL-B

CTL-A

CTL-x

CTL-B

PWMA-I

CTL-A

= Interlocks satisfied; active registers

will be updated at the end of the current

X = Either channel A or channel B register

PWMA-D

RA = RB

PWM cycle

≠ RB

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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